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Intel® Stratix®  10  GX/SX Device

Overview

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Contents

1.  Intel® Stratix® 10 GX/SX Device Overview.................................................................... 3

    1.1.   Intel Stratix 10 GX/SX Family Variants.....................................................................4

           1.1.1. Available Options....................................................................................... 6

    1.2. Innovations in Intel Stratix 10 FPGAs and SoCs......................................................... 6

    1.3.   FPGA and SoC Features Summary...........................................................................8

    1.4. Intel Stratix 10 Block Diagram............................................................................... 11

    1.5.   Intel Stratix 10 FPGA and SoC Family Plan..............................................................11

    1.6. Intel Hyperflex Core Architecture........................................................................... 14

    1.7. Heterogeneous 3D SiP Transceiver Tiles.................................................................. 15

    1.8.   Intel Stratix 10 Transceivers................................................................................. 16

           1.8.1.   PMA Features......................................................................................... 17

           1.8.2.   PCS Features..........................................................................................19
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    1.9.   PCI Express Gen1/Gen2/Gen3 Hard IP................................................................... 20

    1.10.  Interlaken PCS Hard IP...................................................................................... 20

    1.11.  10G Ethernet Hard IP........................................................................................ 21

    1.12.  External Memory and General Purpose I/O........................................................... 21

    1.13.  Adaptive Logic Module (ALM).............................................................................. 22

    1.14.  Core Clocking................................................................................................... 23

    1.15.  Fractional Synthesis PLLs and I/O PLLs.................................................................24

    1.16.  Internal Embedded Memory................................................................................24

    1.17.  Variable Precision DSP Block............................................................................... 24

    1.18.  Hard Processor System (HPS)............................................................................. 27

           1.18.1.  Key Features of the Intel Stratix 10 HPS...................................................28

    1.19.  Power Management........................................................................................... 31

    1.20.  Device Configuration and Secure Device Manager (SDM)......................................... 31

    1.21.  Device Security..................................................................................................33

    1.22.  Configuration via Protocol Using PCI Express..........................................................33

    1.23.  Partial and Dynamic Reconfiguration.................................................................... 34

    1.24.  Fast Forward Compile......................................................................................... 34

    1.25.  Single Event Upset (SEU) Error Detection and Correction........................................34

    1.26.  Document Revision History for the Intel Stratix 10 GX/SX Device Overview................35

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S10-OVERVIEW | 2019.02.15
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